The present invention relates to an information processor which executes instructions sequentially in a pipeline control system while attaining high speed execution by reducing disturbance in the pipeline.
In the pipeline control system, the execution of instructions is divided into a plurality of stages which are executed in an overlapped manner. FIG. 2A shows the execution in a prior art pipeline control system. D denotes an instruction word decoding stage, A denotes an operand effective address calculation stage, B denotes an operand fetching stage from a main memory, L denotes an operand transfer stage in which the operand fetched from the main memory is transferred to an operand buffer register, and E denotes an execution stage in which an operation inherent to an instruction is executed. The effective address in the stage A is calculated by adding contents of two general purpose registers designated by an index part and a base part of the instruction, respectively (which are called an index register and a base register, respectively) and a displacement which is a portion of the instruction.
In the pipeline control system, when the stage D for one instruction is completed, the stage A for that instruction is started and the stage D for the succeeding instruction is started at the same time. In this manner, a plurality of instructions are sequentially executed in an overlapped manner.
Where an instruction I.sub.1 is to instruct to change a content of a general purpose register, for example, instruct to store an operation result in the general purpose register, and the immediately succeeding instruction I.sub.2 is to designate the same general purpose register as the index register or base register in order to use the content thereof for generating an effective address, and if any high speed execution technique is not used, the effective address calculation stage A for the instruction I.sub.2 must be started after the execution stage E for the instruction I.sub.1 has been completed and the operation result has been stored in that general purpose register, as shown in FIG. 2A. As a result, there exists a three-cycle overhead as shown in FIG. 2A. Where the content of the general purpose register to be used to generate the effective address of the operand is changed by the preceding instruction, it is called an address conflict. Several methods for attaining high speed execution under the address conflict situation have been proposed.
FIG. 2B shows a method disclosed in JP-B-56-46170, in which high speed execution of a succeeding instruction I.sub.2 is attained only when the instruction I.sub.1 which changes the content of the general purpose register is a load-type instruction which instructs to load an operand from main memory into a general purpose register as it is. Specifically, the instruction I.sub.1 is executed, the operand is fetched from the main memory and it is transferred to the operand buffer as well as to a register provided at an input of an address generating adder. Simultaneously with the above transfer, the execution of the effective address generation stage A for the succeeding instruction I.sub.2 is started. In this manner, in parallel with the stage E for the instruction I.sub.1 in which the operand is stored into the general purpose register designated by the instruction I.sub.1, the stage A for the succeeding instruction I.sub.2 is executed. As a result, the overhead is reduced to two cycles as shown in FIG. 2B.
In order to further improve the above method, Japanese patent application 61-191841 filed on Aug. 11, 1986, published as JP-A-63-47834, assigned to the assignee of the present invention and entitled "Instruction Processing Apparatus with Enhanced Execution of An Address-Conflicting Instruction" discloses a method to further accelerate the execution of the address conflict by a succeeding instruction when it meets a certain condition. Specifically, where the general purpose register the content of which is to be changed by the preceding instruction is designated as the index register by the succeeding instruction and the content of the base register designated by the succeeding instruction and the displacement designated by the instruction are both zero, or where the general purpose register the content of which is to be changed by the preceding instruction is designated as the base register by the succeeding instruction and the content of the index register designated by the succeeding instruction and the displacement designated by the instruction are both zero, the operand address needed by the succeeding instruction is equal to the operand itself written by the preceding instruction. Accordingly, in such a case, the address calculation for the succeeding instruction may be omitted to accelerate the execution of the succeeding instruction. Thus, the operand fetched from the main memory for the preceding instruction is transferred directly to the main memory referring address register, and the operand fetch stage L for the succeeding stage is executed based on that operand. As a result, the overhead is reduced to one cycle as shown in FIG. 2C.
In the prior art method shown in FIG. 2B, the high speed execution is attained only when the preceding instruction is a load-type instruction but it is not attained when the preceding instruction is an add instruction or subtract instruction.
In the method shown in FIG. 2C, the high speed execution is attained only when the content of the index register designated by the succeeding instruction and the displacement are both zero, or when the content of the base register and the displacement are both zero. The high speed execution is not attained when both of the index register and the base register designated by the succeeding instruction are used to generate the address. When the instruction which changes the content of the general purpose register is an add/subtract instruction, the operation by an operation unit is required and the overhead is increased by one cycle.